The Authors Present a Mechanism That Reduces Excess Voltage Margin in Microprocessors. They First Demonstrated This Mechanism in an Ibm Power7 Server and Proved Its Effectiveness in The

......Microprocessors must operate reliably across a wide range of environmental conditions and workloads. Selecting an operating voltage high enough to account for worst-case conditions without violating power budgets is a growing challenge. Extra margin in the form of voltage guardband must be included to guarantee proper circuit timing during worst-case voltage droop events, in addition to covering for other variables such as test inaccuracy and aging. However, the voltage droop experienced by the microprocessor’s circuits is much smaller under typical workloads and environmental conditions. Therefore, energy is wasted because the higher voltage needed to ensure worst-case operation results in excess timing margin during normal operation. Instead, it would be preferable to maintain a fixed amount of guardband so that only the necessary energy is expended at any operating condition. To this end, we implemented two cooperating feedback controllers in a prototype Power7 server to operate the microprocessor with a fixed timing margin.Critical-path monitors (CPMs) were previously introduced to Power microprocessors to measure the available timing margin. The first feedback controller couples these CPMs with a digital phase-locked loop (DPLL) in hardware and prevents timing errors induced by voltage changes that happen on short time scales. The second feedback controller, implemented in firmware, adjusts the processor voltage to achieve a desired performance level on a longer time scale. We evaluated many workloads running at a single target frequency and measured a significant reduction in processor power after enabling this active guardband management. We call this technique undervolting because it can achieve the same performance level at a lower voltage. The resulting mechanism reduces power consumption for typical workloads and conditions while still allowing worstcase workloads to operate reliably at the maximum frequency. [3B2-9] mmi2013040035.3d 24/7/013 15:22 Page 35